1. Technical Field
The present invention relates generally to semiconductor integrated circuits, and in particular to such integrated circuits that receive a multi-bit address signal for chip selection or selection of a data register in the integrated circuit.
2. Description of the Background Art
Encoders and decoders employing error detecting and correcting codes (ECC) have been used in integrated circuit memories for correcting data errors. The data errors can be "hard" errors caused by defective memory cells, or they can be "soft" errors caused by alpha particles or by other temporary disturbance. In either case, data errors become more prevalent for high density memories, and therefore it is desirable to provide a degree of error correction coding that may compensate for the expected frequency of the errors. It is also known to signal when the error correcting codes are unable to correct the errors.
In a family of error correcting codes known as "Hamming" codes, a certain number of parity bits are added to each block of data bits to enable a desired number of errors in the block to be corrected. One or more additional parity bits can be added to detect additional errors that might not be corrected. For integrated circuit memories, for example, each block of data may include eight bits, and four parity bits may be added to correct any "single-bit error" occurring in the block. An additional parity bit may be added to detect any "double-bit error." By "single-bit error" it is meant that only one bit in the block is in error. In a similar fashion, a "double-bit error" refers to the occurrence of only two erroneous bits in the block.
Error correcting codes have also been used for protecting the transmission of data and memory addresses over busses in computer systems. But the checking and correcting of memory addresses on a bus is not sufficient to ensure that a memory will be properly addressed. In particular, address bit errors or control faults may occur between the error correction circuits and the memory cells, causing good data to be written to or read from the wrong location in memory. Some protection against this problem has been obtained by writing address checking information into the addressed memory location along with the data. Whenever data is read from memory, the address checking information is compared to the address that was used to read the memory. The address checking information may include the parity of the address used in the memory write operation, and to save memory storage space, this address parity information may be combined with data parity information and stored as part of an error correction code for correcting data errors.
The address checking information can detect a sufficient number of addressing faults to diagnose hardware errors in the address bus and control circuitry. But in general it is not possible to use the address checking information to recover from the addressing fault. Before the fault is detected, good data may have been written over and destroyed by the data written to the wrong memory location. Moreover, if new data is written to an incorrect memory location, the subsequent reading of the correct memory location will return old data, and this error will not be detected by comparison of the address checking information.